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Is this circuitry implemented using only CMOS Technology.
In general, an instrumentation amplifier is required to amplify the difference between two input signals or voltages, V1 and V2, providing high voltage gain.
The common-mode rejection ratio (CMRR) of a differential amplifier is the rejection by the device of unwanted input signals common to both input leads, relative to the wanted difference signal. An ideal differential amplifier would have infinite CMRR; this is not achievable in practice. A high CMRR is required when a differential signal must be amplified in the presence of a possibly large common-mode input.
CMRR =20 log10 |( ADM / ACM )|
where
Differential Mode Half-circuit:
ADM = the amplification of the input signal difference, vi2 - vi1
1. Currents about the symmetry line are equal in value and opposite in sign, (e.g.,Id1 = −Id2).
2. Voltages about the symmetry line are equal in value and opposite in sign, (e.g., Vo1 = -Vo2).
3. Voltage at the summery line is zero.
and
Common Mode Half-circuit:
ACM = the amplification of the input signal average, (vi2 + vi1)/2.
1. Currents about symmetry line are equal, (e.g., id1 = id2).
2. Voltages about the symmetry line are equal, (e.g., vo1 = vo2).
3. No current crosses the symmetry line.
The use of the active load (current mirror) greatly improves the common-mode rejection ratio compared to the resistive load case.
An ideal differential amplifier will have a common mode rejection ration of infinity, however as there’s no such a thing as an “ideal” differential amplifier (matched transistors), is not possible to be achieved in Layout integrated circuits, a basic objective in op-amp design is to minimize the is match between the two signal paths in the input differential pair so that common-mode input signals are rejected to the greatest possible extent. Mismatch affects the performance of the differential pair not only at dc, where it causes nonzero offset voltage, but also at high frequencies where it reduces the common-mode.
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