What's the difference between VHDL and Verilog ?

Verilog is way lot permissive than VHDL and sometimes that costs precious time to figure out the error.

VHDL is heavier with its libraries, data types and casting issues but it's very rigorous.

verilog is similar to c language , easy to learn and there is no library files.

vhdl is similar to pascal,library files are present in vhdl and hard to learn compare to verilog

VHDL is strongly typed determic and more verbose than Verilog. It is self documenting unlike C.

Verilog is weakly typed language like C.

Verilog is used for sythesis where as VHDL generally used for non synthesis

Basic difference being that VHDL is based on Ada & Pascal which are hard core programming language with complex data types etc, whereas Verilog is based on C programming which is quite reverse of VHDL.

Moreover Verilog is case sensitive whereas VHDL is not.

Libraries are not found in Verilog which makes it unfit for higher level programming and hence we use VHDL for that.

Verilog is newer language based on C-language having simpler datatypes whereas VHDL which is based on older language has more complex datatypes. Verilog is easy to learn. But Verilog is case sensitive whereas VHDL isn't.