Which one is more power full programming language VERELOG or VHDL?

VHDL

In general, Verilog is easier to learn than VHDL. This is due, in part, to the popularity of the C programming language, making most programmers familiar with the conventions that are used in Verilog. VHDL is a little bit more difficult to learn and program.

VHDL has the advantage of having a lot more constructs that aid in high-level modeling, and it reflects the actual operation of the device being programmed. Complex data types and packages are very desirable when programming big and complex systems, that might have a lot of functional parts. Verilog has no concept of packages, and all programming must be done with the simple data types that are provided by the programmer.

1. Verilog is based on C, while VHDL is based on Pascal and Ada.

2. Unlike Verilog, VHDL is strongly typed.

3. Ulike VHDL, Verilog is case sensitive.

4. Verilog is easier to learn compared to VHDL.

5. Verilog has very simple data types, while VHDL allows users to create more complex data types.

6. Verilog lacks the library management, like that of VHDL.

For Sure VHDL ,,, That's Why ?!! 

You can produce robust designs and comprehensive test environments with both langauges, for both ASIC and FPGA. However, the two langauges approach the task from different directions; VHDL, intended as a specification langauge, is very exact in its nature and hence very verbose.

But Verilog, intended as a simulation langauge, it much closer to C in style, in that it is terse and elegant to write but requires much more care to avoid nasty bugs.