Job Details:Job Description: Execute physical verification runsets (including DRC, LVS, illegal layer, TUC, fill, LU/IOGNAC, denall, tic, tapein merge, IPC) for Synopsys ICV, Siemens Calibre and Cadence Pegasus on chip level database, mimicking virtual tape-in. Identify/triage clear and meaningful list of discrepancies between the 3 runsets for review and final disposition. Candidate should have good physical verification experience with multiple tape-outs. Folks with clarity of DRC/LVS flows and lower process node is a must. Layout+verifcation(drc/lvs/erc/density etc) Physical Design Verification Runset Quality Checks is the primary job function Debug the DRC/LVS rule deck failures during regressions and document the failures to the development team Developing the layout patterns to check every design rule in the redbook design manual and integrate them into the QA regression suite is the work nature on daily basis. Automation of central regression system and maintain and manage test bench is the crucial job function. Execute physical verification runsets (including DRC, LVS, illegal layer, TUC, fill, LU/IOGNAC, denall, tic, tapein merge, IPC) for Synopsys ICV, Siemens Calibre and Cadence Pegasus on Intel database, mimicking virtual tape-in. Identify/triage clear and meaningful list of discrepancies between the 3 runsets for review and final disposition. Candidate should have good physical verification experience with multiple tape-outs. Folks with clarity of intel flows and process node will be an added plus. Develops, maintains, and ensures quality assurance of process design kit (PDK) collateral, including PDK runset, PDK extraction, and modeling transistors for Intel design teams to enable new processes and methodologies to be followed across Intel's product lines. Develops automation of QA flow methodologies for specific technology nodes to scale up QA coverage. Documents and monitors QA results. May include developing test patterns to quality the physical design rules for correct implementations. Performs validation for PDK library covering collaterals, partition cells, 3DIC packaging, and back end physical design checks. Ensures that the design teams meet the requirements of the process node. Leads root cause analysis for issues related to designing to a specific process technology and continuously drives initiatives to enhance design methodologies. Creates and maintains technology files with symbols, device parameters, Pcells, design verification decks, layouts, process constraints, design rule checks, and/or layout versus schematic runsets for silicon designers to understand the design process. Resolves issues and bugs found within the PDK collateral. Builds test structures and runs simulation, physical verification, and parasitic extraction to ensure proper model and design solutions. May also deliver design flows, guidelines, and tutorials through sample design databases, test chips, and libraries. Collaborates with silicon design, process engineering, and highvolume manufacturing teams to identify new process technologies and ensure new solutions are high quality and ensure ease of use for both internal and external design communities. Works with EDA vendors on tool improvements to enhance performance and add functionality.
Qualifications:B Tech 4 yrs experience or MS 2 yrs in Electrical Electronic engineering is required
Experience with ICV and Calibre Layout verification runsets along with tools like CalibreDRV background is a must
Experience working on 7nm or lower process nodes desired
Strong automation scripting skills are required Tcl PythonPerl
Desire to grow in the physical verification design career path is preferred.Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
